Using the GNU Compiler Collection (GCC): ARM Options (2024)

Generate code for the specified ABI. Permissible values are: ‘apcs-gnu’,‘atpcs’, ‘aapcs’, ‘aapcs-linux’ and ‘iwmmxt’.

Generate a stack frame that is compliant with the ARM Procedure CallStandard for all functions, even if this is not strictly necessary forcorrect execution of the code. Specifying -fomit-frame-pointerwith this option causes the stack frames not to be generated forleaf functions. The default is -mno-apcs-frame.This option is deprecated.

This is a synonym for -mapcs-frame and is deprecated.

Generate code that supports calling between the ARM and Thumbinstruction sets. Without this option, on pre-v5 architectures, thetwo instruction sets cannot be reliably used inside one program. Thedefault is -mno-thumb-interwork, since slightly larger codeis generated when -mthumb-interwork is specified. In AAPCSconfigurations this option is meaningless.

Prevent the reordering of instructions in the function prologue, or themerging of those instruction with the instructions in the function’sbody. This means that all functions start with a recognizable setof instructions (or in fact one of a choice from a small set ofdifferent function prologues), and this information can be used tolocate the start of functions inside an executable piece of code. Thedefault is -msched-prolog.

Specifies which floating-point ABI to use. Permissible valuesare: ‘soft’, ‘softfp’ and ‘hard’.

Specifying ‘soft’ causes GCC to generate output containinglibrary calls for floating-point operations.‘softfp’ allows the generation of code using hardware floating-pointinstructions, but still uses the soft-float calling conventions.‘hard’ allows generation of floating-point instructionsand uses FPU-specific calling conventions.

The default depends on the specific target configuration. Note thatthe hard-float and soft-float ABIs are not link-compatible; you mustcompile your entire program with the same ABI, and link with acompatible set of libraries.

Generate code for a processor running in little-endian mode. This isthe default for all standard configurations.

Generate code for a processor running in big-endian mode; the default isto compile code for a little-endian processor.

This specifies the name of the target ARM architecture. GCC uses thisname to determine what kind of instructions it can emit when generatingassembly code. This option can be used in conjunction with or insteadof the -mcpu= option. Permissible names are: ‘armv2’,‘armv2a’, ‘armv3’, ‘armv3m’, ‘armv4’, ‘armv4t’,‘armv5’, ‘armv5e’, ‘armv5t’, ‘armv5te’,‘armv6’, ‘armv6-m’, ‘armv6j’, ‘armv6k’,‘armv6kz’, ‘armv6s-m’,‘armv6t2’, ‘armv6z’, ‘armv6zk’,‘armv7’, ‘armv7-a’, ‘armv7-m’, ‘armv7-r’, ‘armv7e-m’,‘armv7ve’, ‘armv8-a’, ‘armv8-a+crc’, ‘armv8.1-a’,‘armv8.1-a+crc’, ‘armv8-m.base’, ‘armv8-m.main’,‘armv8-m.main+dsp’, ‘iwmmxt’, ‘iwmmxt2’.

Architecture revisions older than ‘armv4t’ are deprecated.

-march=armv6s-m is the ‘armv6-m’ architecture with support forthe (now mandatory) SVC instruction.

-march=armv6zk is an alias for ‘armv6kz’, existing for backwardscompatibility.

-march=armv7ve is the ‘armv7-a’ architecture with virtualizationextensions.

-march=armv8-a+crc enables code generation for the ARMv8-Aarchitecture together with the optional CRC32 extensions.

-march=armv8.1-a enables compiler support for the ARMv8.1-Aarchitecture. This also enables the features provided by-march=armv8-a+crc.

-march=armv8.2-a enables compiler support for the ARMv8.2-Aarchitecture. This also enables the features provided by-march=armv8.1-a.

-march=armv8.2-a+fp16 enables compiler support for theARMv8.2-A architecture with the optional FP16 instructions extension.This also enables the features provided by -march=armv8.1-aand implies -mfp16-format=ieee.

-march=native causes the compiler to auto-detect the architectureof the build computer. At present, this feature is only supported onGNU/Linux, and not all architectures are recognized. If the auto-detectis unsuccessful the option has no effect.

This option specifies the name of the target ARM processor forwhich GCC should tune the performance of the code.For some ARM implementations better performance can be obtained by usingthis option.Permissible names are: ‘arm2’, ‘arm250’,‘arm3’, ‘arm6’, ‘arm60’, ‘arm600’, ‘arm610’,‘arm620’, ‘arm7’, ‘arm7m’, ‘arm7d’, ‘arm7dm’,‘arm7di’, ‘arm7dmi’, ‘arm70’, ‘arm700’,‘arm700i’, ‘arm710’, ‘arm710c’, ‘arm7100’,‘arm720’,‘arm7500’, ‘arm7500fe’, ‘arm7tdmi’, ‘arm7tdmi-s’,‘arm710t’, ‘arm720t’, ‘arm740t’,‘strongarm’, ‘strongarm110’, ‘strongarm1100’,‘strongarm1110’,‘arm8’, ‘arm810’, ‘arm9’, ‘arm9e’, ‘arm920’,‘arm920t’, ‘arm922t’, ‘arm946e-s’, ‘arm966e-s’,‘arm968e-s’, ‘arm926ej-s’, ‘arm940t’, ‘arm9tdmi’,‘arm10tdmi’, ‘arm1020t’, ‘arm1026ej-s’,‘arm10e’, ‘arm1020e’, ‘arm1022e’,‘arm1136j-s’, ‘arm1136jf-s’, ‘mpcore’, ‘mpcorenovfp’,‘arm1156t2-s’, ‘arm1156t2f-s’, ‘arm1176jz-s’, ‘arm1176jzf-s’,‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’,‘cortex-a9’, ‘cortex-a12’, ‘cortex-a15’, ‘cortex-a17’,‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a57’,‘cortex-a72’, ‘cortex-a73’, ‘cortex-r4’,‘cortex-r4f’, ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’,‘cortex-m33’,‘cortex-m23’,‘cortex-m7’,‘cortex-m4’,‘cortex-m3’,‘cortex-m1’,‘cortex-m0’,‘cortex-m0plus’,‘cortex-m1.small-multiply’,‘cortex-m0.small-multiply’,‘cortex-m0plus.small-multiply’,‘exynos-m1’,‘marvell-pj4’,‘xscale’, ‘iwmmxt’, ‘iwmmxt2’, ‘ep9312’,‘fa526’, ‘fa626’,‘fa606te’, ‘fa626te’, ‘fmp626’, ‘fa726te’,‘xgene1’.

Additionally, this option can specify that GCC should tune the performanceof the code for a big.LITTLE system. Permissible names are:‘cortex-a15.cortex-a7’, ‘cortex-a17.cortex-a7’,‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’,‘cortex-a72.cortex-a35’, ‘cortex-a73.cortex-a53’.

-mtune=generic-arch specifies that GCC should tune theperformance for a blend of processors within architecture arch.The aim is to generate code that run well on the current most popularprocessors, balancing between optimizations that benefit some CPUs in therange, and avoiding performance pitfalls of other CPUs. The effects ofthis option may change in future GCC versions as CPU models come and go.

-mtune=native causes the compiler to auto-detect the CPUof the build computer. At present, this feature is only supported onGNU/Linux, and not all architectures are recognized. If the auto-detect isunsuccessful the option has no effect.

This specifies the name of the target ARM processor. GCC uses this nameto derive the name of the target ARM architecture (as if specifiedby -march) and the ARM processor type for which to tune forperformance (as if specified by -mtune). Where this optionis used in conjunction with -march or -mtune,those options take precedence over the appropriate part of this option.

Permissible names for this option are the same as those for-mtune.

-mcpu=generic-arch is also permissible, and isequivalent to -march=arch -mtune=generic-arch.See -mtune for more information.

-mcpu=native causes the compiler to auto-detect the CPUof the build computer. At present, this feature is only supported onGNU/Linux, and not all architectures are recognized. If the auto-detectis unsuccessful the option has no effect.

This specifies what floating-point hardware (or hardware emulation) isavailable on the target. Permissible names are: ‘vfpv2’, ‘vfpv3’,‘vfpv3-fp16’, ‘vfpv3-d16’, ‘vfpv3-d16-fp16’, ‘vfpv3xd’,‘vfpv3xd-fp16’, ‘neon-vfpv3’, ‘neon-fp16’, ‘vfpv4’,‘vfpv4-d16’, ‘fpv4-sp-d16’, ‘neon-vfpv4’,‘fpv5-d16’, ‘fpv5-sp-d16’,‘fp-armv8’, ‘neon-fp-armv8’ and ‘crypto-neon-fp-armv8’.Note that ‘neon’ is an alias for ‘neon-vfpv3’ and ‘vfp’is an alias for ‘vfpv2’.

If -msoft-float is specified this specifies the format offloating-point values.

If the selected floating-point hardware includes the NEON extension(e.g. -mfpu=‘neon’), note that floating-pointoperations are not generated by GCC’s auto-vectorization pass unless-funsafe-math-optimizations is also specified. This isbecause NEON hardware does not fully implement the IEEE 754 standard forfloating-point arithmetic (in particular denormal values are treated aszero), so the use of NEON instructions may lead to a loss of precision.

You can also set the fpu name at function level by using the target("fpu=") function attributes (see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).

Specify the format of the __fp16 half-precision floating-point type.Permissible names are ‘none’, ‘ieee’, and ‘alternative’;the default is ‘none’, in which case the __fp16 type is notdefined. See Half-Precision, for more information.

The sizes of all structures and unions are rounded up to a multipleof the number of bits set by this option. Permissible values are 8, 32and 64. The default value varies for different toolchains. For the COFFtargeted toolchain the default value is 8. A value of 64 is only allowedif the underlying ABI supports it.

Specifying a larger number can produce faster, more efficient code, butcan also increase the size of the program. Different values are potentiallyincompatible. Code compiled with one value cannot necessarily expect towork with code or libraries compiled with another value, if they exchangeinformation using structures or unions.

Generate a call to the function abort at the end of anoreturn function. It is executed if the function tries toreturn.

Tells the compiler to perform function calls by first loading theaddress of the function into a register and then performing a subroutinecall on this register. This switch is needed if the target functionlies outside of the 64-megabyte addressing range of the offset-basedversion of subroutine call instruction.

Even if this switch is enabled, not all function calls are turnedinto long calls. The heuristic is that static functions, functionsthat have the short_call attribute, functions that are insidethe scope of a #pragma no_long_calls directive, and functions whosedefinitions have already been compiled within the current compilationunit are not turned into long calls. The exceptions to this rule arethat weak function definitions, functions with the long_callattribute or the section attribute, and functions that are withinthe scope of a #pragma long_calls directive are alwaysturned into long calls.

This feature is not enabled by default. Specifying-mno-long-calls restores the default behavior, as doesplacing the function calls within the scope of a #pragmalong_calls_off directive. Note these switches have no effect on howthe compiler generates code to handle function calls via functionpointers.

Treat the register used for PIC addressing as read-only, rather thanloading it in the prologue for each function. The runtime system isresponsible for initializing this register with an appropriate valuebefore execution begins.

Specify the register to be used for PIC addressing.For standard PIC base case, the default is any suitable registerdetermined by compiler. For single PIC base case, the default is‘R9’ if target is EABI based or stack-checking is enabled,otherwise the default is ‘R10’.

Assume that the displacement between the text and data segments is fixedat static link time. This permits using PC-relative addressingoperations to access data known to be in the data segment. Fornon-VxWorks RTP targets, this option is enabled by default. Whendisabled on such targets, it will enable -msingle-pic-base bydefault.

Write the name of each function into the text section, directlypreceding the function prologue. The generated code is similar to this:

 t0 .ascii "arm_poke_function_name", 0 .align t1 .word 0xff000000 + (t1 - t0) arm_poke_function_name mov ip, sp stmfd sp!, {fp, ip, lr, pc} sub fp, ip, #4

When performing a stack backtrace, code can inspect the value ofpc stored at fp + 0. If the trace function then looks atlocation pc - 12 and the top 8 bits are set, then we know thatthere is a function name embedded immediately preceding this locationand has length ((pc[-3]) & 0xff000000).

Select between generating code that executes in ARM and Thumbstates. The default for most configurations is to generate codethat executes in ARM state, but the default can be changed byconfiguring GCC with the --with-mode=stateconfigure option.

You can also override the ARM and Thumb mode for each functionby using the target("thumb") and target("arm") function attributes(see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).

Generate a stack frame that is compliant with the Thumb Procedure CallStandard for all non-leaf functions. (A leaf function is one that doesnot call any other functions.) The default is -mno-tpcs-frame.

Generate a stack frame that is compliant with the Thumb Procedure CallStandard for all leaf functions. (A leaf function is one that doesnot call any other functions.) The default is -mno-apcs-leaf-frame.

Gives all externally visible functions in the file being compiled an ARMinstruction set header which switches to Thumb mode before executing therest of the function. This allows these functions to be called fromnon-interworking code. This option is not valid in AAPCS configurationsbecause interworking is enabled by default.

Allows calls via function pointers (including virtual functions) toexecute correctly regardless of whether the target code has beencompiled for interworking or not. There is a small overhead in the costof executing a function pointer if this option is enabled. This optionis not valid in AAPCS configurations because interworking is enabledby default.

Specify the access model for the thread local storage pointer. The validmodels are ‘soft’, which generates calls to __aeabi_read_tp,‘cp15’, which fetches the thread pointer from cp15 directly(supported in the arm6k architecture), and ‘auto’, which uses thebest available method for the selected processor. The default setting is‘auto’.

Specify the dialect to use for accessing thread local storage. Twodialects are supported—‘gnu’ and ‘gnu2’. The‘gnu’ dialect selects the original GNU scheme for supportinglocal and global dynamic TLS models. The ‘gnu2’ dialectselects the GNU descriptor scheme, which provides better performancefor shared libraries. The GNU descriptor scheme is compatible withthe original scheme, but does require new assembler, linker andlibrary support. Initial and local exec TLS models are unaffected bythis option and always use the original scheme.

Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).This is enabled by default on targets (uClinux, SymbianOS) where the runtimeloader imposes this restriction, and when -fpic or -fPICis specified.

Some Cortex-M3 cores can cause data corruption when ldrd instructionswith overlapping destination and base registers are used. This option avoidsgenerating these instructions. This option is enabled by default when-mcpu=cortex-m3 is specified.

Enables (or disables) reading and writing of 16- and 32- bit valuesfrom addresses that are not 16- or 32- bit aligned. By defaultunaligned access is disabled for all pre-ARMv6, all ARMv6-M and forARMv8-M Baseline architectures, and enabled for all otherarchitectures. If unaligned access is not enabled then words in packeddata structures are accessed a byte at a time.

The ARM attribute Tag_CPU_unaligned_access is set in thegenerated object file to either true or false, depending upon thesetting of this option. If unaligned access is enabled then thepreprocessor symbol __ARM_FEATURE_UNALIGNED is alsodefined.

Enables using Neon to handle scalar 64-bits operations. This isdisabled by default since the cost of moving data from core registersto Neon is high.

Assume loading data from flash is slower than fetching instruction.Therefore literal load is minimized for better performance.This option is only supported when compiling for ARMv7 M-profile andoff by default.

Assume inline assembler is using unified asm syntax. The default iscurrently off which implies divided syntax. This option has no impacton Thumb2. However, this may change in future releases of GCC.Divided syntax should be considered deprecated.

Restricts generation of IT blocks to conform to the rules of ARMv8.IT blocks can only contain a single 16-bit instruction from a selectset of instructions. This option is on by default for ARMv8 Thumb mode.

Print CPU tuning information as comment in assembler file. This isan option used only for regression testing of the compiler and notintended for ordinary use in compiling code. This option is disabledby default.

Do not allow constant data to be placed in code sections.Additionally, when compiling for ELF object format give all text sections theELF processor-specific section attribute SHF_ARM_PURECODE. This optionis only available when generating non-pic code for ARMv7-M targets.

Generate secure code as per the "ARMv8-M Security Extensions: Requirements onDevelopment Tools Engineering Specification", which can be found onhttp://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf.